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Rev. 1.00, 05/04, page 202 of 544
10.3.6 Time Constant Register (TCORC)
TCORC is an 8-bit readable/writable register. The sum of contents of TCORC and TICR is always
compared with TCNT. When a match is detected, a compare-match C signal is generated.
However, comparison at the T2 state in the write cycle to TCORC and at the input capture cycle of
TICR is disabled. TCORC is initialized to H'FF.
10.3.7 Input Capture Registers R and F (TICRR, TICRF, TICRR_A and TICRF_A)
TICRR and TICRF are 8-bit read-only registers. While the ICST bit in TCONRI (TCRAB) is set
to 1, the contents of TCNT are transferred at the rising edge and falling edge of the external reset
input (TMRIX and TMRIA) in that order. The ICST bit is cleared to 0 when one capture operation
ends. TICRR and TICRF are initialized to H'00.
10.3.8 Timer Input Select Register (TISR and TISR_B)
TISR permits or prohibits a signal source of external clock/reset input for the counter.
Bit Bit Name
Initial
Value R/W Description
7 to 1 — All 1 R/(W) Reserved
The initial value should not be changed.
0 IS 0 R/W Input Select
Selects a timer clock/reset input pin (TMIn) as the
signal source of external clock/reset input for the
TMR_n counter.
0: TMIn (TMCIn/TMRIn) is prohibited
1: TMIn (TMCIn/TMRIn) is permitted for input
Note: n = Y and B