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Rev. 1.00, 05/04, page 374 of 544
• HICR1
R/W
Bit Bit Name
Initial
Value
Slave Host Description
7 LPCBSY 0 R/W — LPC Busy
Indicates that the host interface is processing a transfer
cycle.
0: Host interface is in transfer cycle wait state
• Bus idle, or transfer cycle not subject to processing
is in progress
• Cycle type or address indeterminate during transfer
cycle
[Clearing conditions]
• LPC hardware reset or LPC software reset
• LPC hardware shutdown or LPC software shutdown
• Forced termination (abort) of transfer cycle subject
to processing
• Normal termination of transfer cycle subject to
processing
1: Host interface is performing transfer cycle processing
[Setting condition]
• Match of cycle type and address
6 CLKREQ 0 R — LCLK Request
Indicates that the host interface's SERIRQ output is
requesting a restart of LCLK.
0: No LCLK restart request
[Clearing conditions]
• LPC hardware reset or LPC software reset
• LPC hardware shutdown or LPC software shutdown
• SERIRQ is set to continuous mode
• There are no further interrupts for transfer to the
host in quiet mode
1: LCLK restart request issued
[Setting condition]
• In quiet mode, SERIRQ interrupt output becomes
necessary while LCLK is stopped