Filter
Top Products
Rev. 1.00, 05/04, page 474 of 544
20.7 Watch Mode
The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed
mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR
cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1.
In watch mode, the CPU is stopped and peripheral modules other than WDT_1 are also stopped.
The contents of the CPU's internal registers, several on-chip peripheral module registers, and on-
chip RAM data are retained and the I/O ports retain their values before transition as long as the
prescribed voltage is supplied.
Watch mode is exited by an interrupt (WOVI1, NMI, IRQ0 to IRQ2, IRQ6, or IRQ7), RES pin
input, or STBY pin input.
When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or
medium-speed mode when the LSON bit in LPWRCR cleared to 0 or to subactive mode when the
LSON bit is set to 1. When a transition is made to high-speed mode, a stable clock is supplied to
the entire LSI and interrupt exception handling starts after the time set in the STS2 to STS0 bits in
SBYCR has elapsed. In the case of an IRQ0 to IRQ2, IRQ6, or IRQ7 interrupt, watch mode is not
exited if the corresponding enable bit has been cleared to 0. In the case of interrupts from the on-
chip peripheral modules, watch mode is not exited if the interrupt enable register has been set to
disable the reception of that interrupt, or the interrupt is masked by the CPU.
When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of
system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must
be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock
oscillation stabilization time has passed, the CPU begins reset exception handling.
If the STBY pin is driven low, the LSI enters hardware standby mode.