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Rev. 1.00, 05/04, page 409 of 544
Table 15.8 summarizes the methods of setting and clearing these bits, and figure 15.8 shows the
processing flowchart.
Table 15.8 HIRQ Setting and Clearing Conditions
Host Interrupt Setting Condition Clearing Condition
HIRQ1
(independent
from IEDIR)
Internal CPU writes to ODR1, then reads 0
from bit IRQ1E1 and writes 1
Internal CPU writes 0 to bit
IRQ1E1, or host reads ODR1
HIRQ12
(independent
from IEDIR)
Internal CPU writes to ODR1, then reads 0
from bit IRQ12E1 and writes 1
Internal CPU writes 0 to bit
IRQ12E1, or host reads ODR1
SMI
(IEDIR = 0)
Internal CPU
• writes to ODR2, then reads 0 from bit
SMIE2 and writes 1
• writes to ODR3, then reads 0 from bit
SMIE3A and writes 1
• writes to TWR15, then reads 0 from bit
SMIE3B and writes 1
Internal CPU
• writes 0 to bit SMIE2, or host
reads ODR2
• writes 0 to bit SMIE3A, or host
reads ODR3
• writes 0 to bit SMIE3B, or host
reads TWR15
SMI
(IEDIR = 1)
Internal CPU
• reads 0 from bit SMIE2, then writes 1
• reads 0 from bit SMIE3A, then writes 1
• reads 0 from bit SMIE3B, then writes 1
Internal CPU
• writes 0 to bit SMIE2
• writes 0 to bit SMIE3A
• writes 0 to bit SMIE3B
HIRQi
(i = 6, 9, 10, 11)
(IEDIR = 0)
Internal CPU
• writes to ODR2, then reads 0 from bit
IRQiE2 and writes 1
• writes to ODR3, then reads 0 from bit
IRQiE3 and writes 1
Internal CPU
• writes 0 to bit IRQiE2, or host
reads ODR2
• CPU writes 0 to bit IRQiE3, or
host reads ODR3
HIRQi
(i = 6, 9, 10, 11)
(IEDIR = 1)
Internal CPU
• reads 0 from bit IRQiE2, then writes 1
• reads 0 from bit IRQiE3, then writes 1
Internal CPU
• writes 0 to bit IRQiE2
• writes 0 to bit IRQiE3