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Rev. 1.00, 05/04, page 240 of 544
Bit Bit Name
Initial
Value R/W Description
3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is
disabled. On receiving data in which the multiprocessor
bit is 1, this bit is automatically cleared and normal
reception is resumed. For details, refer to section 12.5,
Multiprocessor Communication Function.
2 TEIE 0 R/W Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
1
0
CKE1
CKE0
0
0
R/W
R/W
Clock Enable 1, 0
These bits select the clock source and SCK pin
function.
Asynchronous mode
00: Internal clock
(SCK pin functions as I/O port.)
01: Internal clock
(Outputs a clock of the same frequency as the bit
rate from the SCK pin.)
1X: External clock
(Inputs a clock with a frequency 16 times the bit
rate from the SCK pin.)
Clocked synchronous mode
0X: Internal clock (SCK pin functions as clock output.)
1X: External clock (SCK pin functions as clock input.)
[Legend]
X: Don't care