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AMD Geode™ SC2200 Processor Data Book 17
2
Architecture Overview 32580B
2.0Architecture Overview
As illustrated in Figure 1-1 on page 13, the SC2200 pro-
cessor contains the following modules in one integrated
device:
• GX1 Module:
— Combines advanced CPU performance with MMX
support, fully accelerated 2D graphics, a 64-bit
synchronous DRAM (SDRAM) interface and a PCI
bus controller. Integrates GX1 silicon revision 8.1.1.
• Video Processor Module:
— A low-power CRT and TFT support module with a
video input port, and a hardware video accelerator
for scaling, filtering and color space conversion.
• Core Logic Module:
— Includes PC/AT functionality, an IDE interface, a
Universal Serial Bus (USB) interface, ACPI 1.0
compliant power management, and an audio codec
interface.
• SuperI/O Module:
— Includes two Serial Ports, an Infrared (IR) Port, a
Parallel Port, two ACCESS.bus interfaces, and a
Real-Time Clock (RTC).
2.1 GX1 Module
The GX1 processor (silicon revision 8.1.1) is the central
module of the SC2200. For detailed information regarding
the GX1 module, refer to the AMD Geode™ GX1 Proces-
sor Data Book and the AMD Geode™ GX1 Processor Sili-
con Revision 8.1.1 Specification Update document.
The device ID of the SC2200 processor is contained in the
GX1 module. Software can detect the revision by reading
the DIR0 and DIR1 Configuration registers (see Configura-
tion registers in the AMD Geode™ GX1 Processor Data
Book). The AMD Geode™ SC2200 Processor Specifica-
tion Update document contains the specific values.
2.1.1 Memory Controller
The GX1 module is connected to external SDRAM devices.
For more information see Section 3.4.2 "Memory Interface
Signals" on page 54, and the “Memory Controller” chapter
in the AMD Geode™ GX1 Processor Data Book.
There are some differences in the memory controller of the
SC2200 processor and the standalone GX1 processor’s
memory controller:
1) There is drive strength/slew control in the SC2200 that
is not in the GX1. The bits that control this function are
in the MC_MEM_CNTRL1 and MC_MEM_CNTRL2
registers. In the GX1 processor, these bits are marked
as reserved.
2) The SC2200 supports two banks of memory. The GX1
supports four banks of memory. In addition, the
SC2200 supports a maximum of eight devices and the
GX1 supports up to 32 devices. With this difference,
the MC_BANK_CFG register is different.
Table 2-1 summarizes the 32-bit registers contained in the
SC2200’s memory controller. Table 2-2 gives detailed reg-
ister/bit formats.