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314 AMD Geode™ SC2200 Processor Data Book
Core Logic Module - ISA Legacy Register Space
32580B
2 IRQ2 / IRQ10 Mask.
0: Not Masked.
1: Mask.
1 IRQ1 / IRQ9 Mask.
0: Not Masked.
1: Mask.
0 IRQ0 / IRQ8 Mask.
0: Not Masked.
1: Mask.
I/O Port 020h / 0A0h Master / Slave PIC OCW2 (WO)
7:5 Rotate/EOI Codes.
000: Clear rotate in Auto EOI mode 100: Set rotate in Auto EOI mode
001: Non-specific EOI 101: Rotate on non-specific EOI command
010: No operation 110: Set priority command (bits [2:0] must be valid)
011: Specific EOI (bits [2:0] must be valid) 111: Rotate on specific EOI command
4:3 Reserved. Must be set to 0.
2:0 IRQ Number (000-111).
I/O Port 020h / 0A0h Master / Slave PIC OCW3 (WO)
7 Reserved. Must be set to 0.
6:5 Special Mask Mode.
00: No operation.
01: No operation.
10: Reset Special Mask Mode.
11: Set Special Mask Mode.
4 Reserved. Must be set to 0.
3 Reserved. Must be set to 1.
2 Poll Command.
0: Disable.
1: Enable.
1:0 Register Read Mode.
00: No operation.
01: No operation.
10: Read interrupt request register on next read of Port 20h.
11: Read interrupt service register on next read of Port 20h.
I/O Port 020h / 0A0h Master / Slave PIC Interrupt Request and Service Registers
for OCW3 Commands (RO)
The function of this register is set with bits [1:0] in a write to 020h.
Interrupt Request Register
7 IRQ7 / IRQ15 Pending.
0: Yes.
1: No.
6 IRQ6 / IRQ14 Pending.
0: Yes.
1: No.
5 IRQ5 / IRQ13 Pending.
0: Yes.
1: No.
4 IRQ4 / IRQ12 Pending.
0: Yes.
1: No.
Table 6-46. Programmable Interrupt Controller Registers (Continued)
Bit Description