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AMD Geode™ SC2200 Processor Data Book 337
Video Processor Module
32580B
7.2.7 Integrated PLL
The integrated (CRT) PLL can generate frequencies up to
135 MHz from a single 27 MHz source. The clock fre-
quency is programmable using two registers. Figure 7-15
shows the block diagram of the Video Processor integrated
PLL.
F
REF
is 27 MHz, generated by an external crystal and an
integrated oscillator. F
OUT
is calculated from:
F
OUT
= (m + 1) / (n+ 1) x F
REF
The integrated PLL can generate any frequency by writing
into the CRT-m and CRT-n bit fields (FBAR0+Memory Off-
set 2Ch). Additionally, 16 preprogrammed VGA frequencies
can be selected via the PLL Clock Select register
(F4BAR0+Memory Offset 2Ch[19:16]), if the crystal oscilla-
tor has a frequency of 27 MHz. This PLL can be powered
down via the Miscellaneous register (F4BAR0+Memory
Offset 28h[12]).
Figure 7-15. PLL Block Diagram
F
REF
F
OUT
n
Phase
Charge
m
VCO
Compare
Divider
Divider
Pump
Loop
Filter
Out
Divide