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296 AMD Geode™ SC2200 Processor Data Book
Core Logic Module - USB Controller Registers - PCIUSB
32580B
6 RootHubStatusChange. This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus register has
changed.
5 FrameNumberOverflow. Set when bit 15 of FrameNumber changes value.
4 UnrecoverableError (Read Only). This event is not implemented and is hard-coded to 0. Writes are ignored.
3 ResumeDetected. Set when HC detects resume signaling on a downstream port.
2 StartOfFrame. Set when the Frame Management block signals a Start of Frame event.
1 WritebackDoneHead. Set after the HC has written HcDoneHead to HccaDoneHead.
0 SchedulingOverrun. Set when the List Processor determines a Schedule Overrun has occurred.
Note: All bits are set by hardware and cleared by software.
Offset 10h-13h HcInterruptEnable Register (R/W) Reset Value = 00000000h
31 MasterInterruptEnable. This bit is a global interrupt enable. A write of 1 allows interrupts to be enabled via the specific
enable bits listed above.
30 OwnershipChangeEnable.
0: Ignore.
1: Enable interrupt generation due to Ownership Change.
29:7 Reserved. Read/Write 0s.
6 RootHubStatusChangeEnable.
0: Ignore.
1: Enable interrupt generation due to Root Hub Status Change.
5 FrameNumberOverflowEnable.
0: Ignore.
1: Enable interrupt generation due to Frame Number Overflow.
4 UnrecoverableErrorEnable. This event is not implemented. All writes to this bit are ignored.
3 ResumeDetectedEnable.
0: Ignore.
1: Enable interrupt generation due to Resume Detected.
2 StartOfFrameEnable.
0: Ignore.
1: Enable interrupt generation due to Start of Frame.
1 WritebackDoneHeadEnable.
0: Ignore.
1: Enable interrupt generation due to Writeback Done Head.
0 SchedulingOverrunEnable.
0: Ignore.
1: Enable interrupt generation due to Scheduling Overrun.
Note: Writing a 1 to a bit in this register sets the corresponding bit, while writing a 0 leaves the bit unchanged.
Offset 14h-17h HcInterruptDisable Register (R/W) Reset Value = 00000000h
31 MasterInterruptEnable. Global interrupt disable. A write of 1 disables all interrupts.
30 OwnershipChangeEnable.
0: Ignore.
1: Disable interrupt generation due to Ownership Change.
29:7 Reserved. Read/Write 0s.
Table 6-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
Bit Description