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280 AMD Geode™ SC2200 Processor Data Book
Core Logic Module - Audio Registers - Function 3
32580B
20 Mask Internal IRQ4. (Write Only)
0: Disable.
1: Enable.
19 Mask Internal IRQ3. (Write Only)
0: Disable.
1: Enable.
18 Reserved. (Write Only) Must be set to 0.
17 Mask Internal IRQ1. (Write Only)
0: Disable.
1: Enable.
16 Reserved. (Write Only) Must be set to 0.
15 Assert Masked Internal IRQ15.
0: Disable.
1: Enable.
14 Assert Masked Internal IRQ14.
0: Disable.
1: Enable.
13 Reserved. Set to 0.
12 Assert Masked Internal IRQ12.
0: Disable.
1: Enable.
11 Assert masked internal IRQ11.
0: Disable.
1: Enable.
10 Assert Masked Internal IRQ10.
0: Disable.
1: Enable.
9 Assert Masked Internal IRQ9.
0: Disable.
1: Enable.
8 Reserved. Set to 0.
7 Assert Masked Internal IRQ7.
0: Disable.
1: Enable.
6 Reserved. Set to 0.
5 Assert Masked Internal IRQ5.
0: Disable.
1: Enable.
4 Assert Masked Internal IRQ4.
0: Disable.
1: Enable.
3 Assert Masked Internal IRQ3.
0: Disable.
1: Enable.
2 Reserved. Must be set to 0.
Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)
Bit Description