Filter
Top Products
318 AMD Geode™ SC2200 Processor Data Book
Core Logic Module - ISA Legacy Register Space
32580B
3 IRQ3 Edge or Level Sensitive Select. Selects PIC IRQ3 sensitivity configuration.
0: Edge.
1: Level.
2:0 Reserved. Must be set to 0.
I/O Port 4D1h Interrupt Edge/Level Select Register 2 (R/W) Reset Value: 00h
Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides the setting for bits 7:6 and 4:1 in this register.
2. Bits [7:6] and [4:1] in this register are used to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive
(shared).
7 IRQ15 Edge or Level Sensitive Select. Selects PIC IRQ15 sensitivity configuration.
0: Edge.
1: Level.
6 IRQ14 Edge or Level Sensitive Select. Selects PIC IRQ14 sensitivity configuration.
0: Edge.
1: Level.
5 Reserved. Must be set to 0.
4 IRQ12 Edge or Level Sensitive Select. Selects PIC IRQ12 sensitivity configuration.
0: Edge.
1: Level.
3 IRQ11 Edge or Level Sensitive Select. Selects PIC IRQ11 sensitivity configuration.
0: Edge.
1: Level.
2 IRQ10 Edge or Level Sensitive Select. Selects PIC IRQ10 sensitivity configuration.
0: Edge.
1: Level.
1 IRQ9 Edge or Level Sensitive Select. Selects PIC IRQ9 sensitivity configuration.
0: Edge.
1: Level.
0 Reserved. Must be set to 0.
Table 6-49. Miscellaneous Registers (Continued)
Bit Description