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centralMemoryTest
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Telnet Commands
centralMemoryTest
Perform a bit write/read test of the ASIC central memory.
Syntax
centralMemoryTest [passCount, dataType, dataSeed]
Availability Admin
Description Use this command to verify the address and data bus of the ASIC
SRAMs that serve as the central memory.
This command may not be executed on an enabled switch. You must first
disable the switch using the switchDisable command.
The test consists of 6 subtests:
Subtest 1
The BISR subtest executes the Built-In-Self-Repair (BISR) circuitry in
each ASIC. The BISR executes its own BIST, and cells found bad are
replaced by redundant rows provided in each SRAM in the ASIC.
Once replaced, the BIST is executed again.
The firmware merely sets up the hardware for the BISR/BIST
operation and checks the results. If the done bit in each SRAM is not
set within a time-out period, it reports the DIAG-CMBISRTO. If any
of the SRAMs within the ASIC fails to map out the bad rows, its fail
bit is set and the DIAG-CMBISRF error generated.
Subtest 2
The data write/read subtest executes the address and data bus
verifications by running a specified unique ramp pattern D to all
SRAMs in all ASICs in the switch. When all SRAMs are written with
pattern D, the SRAMs are read and compared against the data
previously written. The above step is repeated with the
complemented pattern ~D to ensure that each data bit is toggled
during the test.
The default pattern used (by POST also) is a QUAD_RAMP with a
seed value of 0.
Subtest 3
The ASIC-to-ASIC connection subtest verifies that any port can read
the data from any of the ASICs in the switch; thus verifying both the
logic transmitting and receiving the data and the physical transmit
data paths on the main board connecting all the ASICs to each other.