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16-Bit Timer Setup Examples
MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
109
Panasonic
TM0BR (example) x’00FE10’
Do not change the clock source
once you select it. Selecting the
clock source while you set up
the count operation control will
corrupt the value in the binary
counter.
3. Set the TM0LD bit of the TM0MD register to 1. This loads the value in the
base register to the binary counter. At the same time, select the clock source
as B
OSC
/4 by writing b’00’ to TM0S[1:0].
TM0MD (example) x’00FE20’
In the bank and linear address-
ing versions of the MN102
series, it was necessary to set
TM0EN and TM0LD to 0
between steps 3 and 4, to
ensure stable operation. This is
unnecessary in the high-speed
linear addressing version.
Use the MOV instruction for this
setup and only use 16-bit write
operations.
This step stops the TM4BC
count and clears both TM4BC
and the S-R flip-flop to 0.
4. Set TM0LD to 0 and TM0EN to 1. This starts the timer. Counting begins at
the start of the next cycle. When the binary counter reaches 0 and loads the
value x’01’ from the base register, in preparation for the next count, a timer 0
underflow interrupt request is sent to the CPU.
To set up timer 4:
1. Set the operating mode in the timer 4 mode register (TM4MD). Disable
timer 4 counting and interrupts. Select up counting. Set the TM4NLP bit to 0
to select looped counting from 0 to x’FFFF’. Select timer 0 underflow as the
clock source.
TM4MD (example) x’00FE80’
2. Set the TM4NLD bit of the TM4MD register to 1 and the TM4EN bit to 0.
This enables TM4BC and the S-R flip-flop. This step ensures stable opera-
tion. If it is omitted, the binary counter may not count the first cycle. Do not
change any other operating modes during this step.
When TM4MD[1:0] = b’11’ (dur-
ing capture), TM4CA and
TM4CB become read-only regis-
ters. To write to TM4CA or
TM4CB, you must first set
TM4MD[1:0] = b’00’.
3. Set TM4NLD and TM4EN to 1. This starts the timer. Counting begins at the
start of the next cycle.
To enable timer 4 capture B interrupts:
Cancel all existing interrupt requests. Next, set the interrupt priority level in the
TM4CBLV[2:0] bits of the TM4CBICH register (levels 0 to 6), set the TM4BIE
bit to 1, and set the TM4BIR bit of TM4CBICL to 0. From this point on, an
interrupt request is generated whenever a timer 4 capture B event occurs.
Bit:76543210
TM0
BR7
TM0
BR6
TM0
BR5
TM0
BR4
TM0
BR3
TM0
BR2
TM0
BR1
TM0
BR0
Setting:00000001
Bit:76543210
TM0
EN
TM0
LD
————
TM0
S1
TM0
S0
Setting:01000000
Bit:1514131211109876543210
TM4
EN
TM4
NLD
——
TM4
UD1
TM4
UD0
TM4
TGE
TM4
ONE
TM4
MD1
TM4
MD0
TM4
ECLR
TM4
LP
TM4
ASEL
TM4
S2
TM4
S1
TM4
S0
Setting:0000000011001 or 0000
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