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Interrupts
Interrupt Control Registers
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
66
Panasonic
SCR0ICH: Serial 0 Reception End Interrupt Control Register (High) x’00FC85’
SCR0ICH enables serial 0 reception end interrupts. It is an 8-bit access
register. Use the MOVB instruction to access it.
The priority level for serial 0 reception end interrupts is written to the
ANLV[2:0] field of the ANICH register.
SCR0IE: Serial 0 reception end interrupt enable flag
0: Disable
1: Enable
VBIVICL: VBIVSYNC (1) Interrupt Control Register (Low) x’00FC88’
VBIVICL detects and requests VBIVSYNC (1) interrupts. It is an 8-bit
access register. Use the MOVB instruction to access it.
VBIVIR: VBIVSYNC (1) interrupt request flag
0: No interrupt requested
1: Interrupt requested
VBIVID: VBIVSYNC (1) interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
VBIVICH: VBIVSYNC (1) Interrupt Control Register (High) x’00FC89’
VBIVICH sets the priority level for and enables VBIVSYNC (1) inter-
rupts. It is an 8-bit access register. Use the MOVB instruction to access it.
VBIVLV[2:0]: VBIVSYNC (1) interrupt priority level
Sets the priority from 0 to 6.
VBIVIE: VBIVSYNC (1) interrupt enable flag
0: Disable
1: Enable
Bit:76543210
———————
SCR0
IE
Reset:00000000
R/W:RRRRRRRR/W
Bit:76543210
———VBIVIR———VBIVID
Reset:00000000
R/W:RRRR/WRRRR
Bit:76543210
—
VBIV
LV 2
VBIV
LV 1
VBIV
LV 0
———
VBIV
IE
Reset:00000000
R/W: R R/W R/W R/W R R R R/W