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H Counter
Description
MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
307
Panasonic
14 H Counter
14.1 Description
The MN102H75K/85K contains two H counter circuits that can be used to count
the HSYNC signal. Each H counter consists of a 10-bit counter and 10-bit
register.
14.2 Block Diagram
14.3 H Counter Operation
Figure 14-2 provides a schematic diagram of an example counter operation.
Figure 14-1 H Counter Block Diagram
Note: In this example, HI0 is active high and VSYNC
is active low.
Figure 14-2 H Counter Operation Example
Divider
Polarity
switch
PWM10
waveform
M
U
X
VSYNC
VI0
10-bit register
10-bit counter
HI0/HI1
Data bus
1024 µs
2048 µs
4096 µs
8192 µs
Reset
Latch
Count source
Selected in SELR[20:00]/SELR[21:01] fields
of HCCNT0/HCCNT1 registers.
Selected in REDG0/REDG1 bits
of HCCNT0/HCCNT1 registers.
Selected in SEDG0/SEDG1 bits
of HCCNT0/HCCNT1 registers.
HI0 for H counter 0, and
HI1 for H counter 1
341-µs signal
from PWM block
Polarity
switch
HI0
Count
VSYNC
Register
setting
N-2 N-1 N 1 2 3
N
Latched on the falling edge of VSYNC
Latch
HI0 rising-edge count
0