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Field Detection Circuit
MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
201
Panasonic
7.14 Field Detection Circuit
7.14.1 Block Diagram
7.14.2 Description
The 7-bit field counter in this block resets every HSYNC interval to count the
system clock. At each VSYNC interval, the 4 MSBs of the 7-bit counter are alter-
nately loaded (made readable) to bits 7 to 4 (N2) and 3 to 0 (N1) of the EVOD
register (x’007F0E’). The comparator compares the N1 and N2 values and
outputs the results to the EOMON bit of EVOD. The OSD identifies the field that
sets EOMON to 1 as the display start field. Table 7-15 shows the criteria that the
comparator uses.
By reading the FRMON bit of EVOD, the OSD can determine which register the
4 MSBs will load to on the next VSYNC input.
To ensure that the display starts at the right field, you must also set the EOSEL
bit of EVOD so that EOMON becomes 1 at the display start field.
Figure 7-36 Field Detection Circuit Block Diagram
Figure 7-37 Field Detection Timing
Divide
by 3
7-bit counter
R
System
clock
T-FF
D-FF x 4 (N1)
4LOADN1
VSYNC
leading
edge detection
4Upper 4 bits
D-FF x 4 (N2)
x’007F0E’ EVOD (FREG[23:20])
x’007F0E’ EVOD (FREG[13:10])
HSYNC Database
Comparator
Vertical display
controller
N2CNT
4LOADN2
4
N1CNT
EOMON
EOSEL
FRMON
4
VSYNC
HSYNC
FRMON
Load value to FREG2
Field counter value
0
Load value to FREG1