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I/O Port Circuit Diagrams
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
262
Panasonic
Figure 11-11 P55 and P56 (Port 5)
P5PUP5
0: Pullup off
1: Pullup on
P5MD5
0: P55
1: SBO0
P5DIR5
0: Port input
1: Port output
0: Push-pull
1: Open-drain
(For I
2
C mode)
(PCNT0) bit 12
ODASCI0
P5OUT5
P5IN5
P5IN6
SBI0
0: Port low output
1: Port high output
Pin
0
1
M
U
X
1
M
U
X
1
0
M
U
X
Schmidt trigger
P55/
SBO0
Pin
P56/
SBI0/
SBD0
P5PUP6
0: Pullup off
1: Pullup on
0: P56
1: SBI0/SBD0
P5MD6
0: 3-line (SBI0,SBO0,SBT0)
1: 2-line (SBD0,SBT0)
0: Port input
1: Port output
P5DIR6
0
P5OUT6
0: Port low output
1: Port high output
Schmidt trigger
SBO0
(PCNT0) bit 10
SIFSEL0
SBO0