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8-Bit Timer Block Diagrams
MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
79
Panasonic
4.3 8-Bit Timer Block Diagrams
Figure 4-3 Timer 0 Block Diagram
Figure 4-4 Timer 1 Block Diagram
(FE10)
(FE00)
TM0MD
(FE20)
B
OSC
/4
B
OSC
/64
B
OSC
/412
TM0I pin
Multiplexer
0
1
2
3
Timer 0
underflow
interrupt
Underflow
Reload
Timer 0 base register
TM0BR
TM0LD
TM0EN
TM0S0
TM0S1
Load
Count
8
Timer 0 binary counter
TM0BC
88
Data bus
8
1/2
Reset
P2MD7,P2DIR7 setting
TM0O pin
(FE11)
(FE01)
TM1MD
(FE21)
0
1
2
3
Underflow
Reload
Timer 1 base register
TM1BR
TM1LD
TM1EN
TM1S0
TM1S1
Load
Count
8
Timer 1 binary counter
TM1BC
8 88
Data bus
B
OSC
/4
B
OSC
/64
Cascade from timer 0
TM1I pin
Multiplexer
Timer 1
underflow
interrupt
1/2
P4MD1,P4DIR1 setting
TM1O pin
Reset