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Interrupts
Interrupt Control Registers
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
68
Panasonic
TM3UDICH: Timer 3 Underflow Interrupt Control Register (High) x’00FC8D’
TM3UDICH enables timer 3 underflow interrupts. It is an 8-bit access reg-
ister. Use the MOVB instruction to access it.
The priority level for timer 3 underflow interrupts is written to the
VBIVLV[2:0] field of the VBIVICH register.
TM3UDIE: Timer 3 underflow interrupt enable flag
0: Disable
1: Enable
OSDGICL: OSD (Graphics) Interrupt Control Register (Low) x’00FC90’
OSDGICL detects and requests OSD (graphics) interrupts. It is an 8-bit
access register. Use the MOVB instruction to access it.
OSDGIR: OSD (graphics) interrupt request flag
0: No interrupt requested
1: Interrupt requested
OSDGID: OSD (graphics) interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
OSDGICH: OSD (Graphics) Interrupt Control Register (High) x’00FC91’
OSDGICH sets the priority level for and enables OSD (graphics) inter-
rupts. It is an 8-bit access register. Use the MOVB instruction to access it.
OSDGLV[2:0]: OSD (graphics) interrupt priority level
Sets the priority from 0 to 6.
OSDGIE: OSD (graphics) interrupt enable flag
0: Disable
1: Enable
Bit:76543210
———————
TM3UD
IE
Reset:00000000
R/W:RRRRRRRR/W
Bit:76543210
———
OSDG
IR
———
OSDG
ID
Reset:00000000
R/W:RRRR/WRRRR
Bit:76543210
—
OSDG
LV 2
OSDG
LV 1
OSDG
LV 0
———
OSDG
IE
Reset:00000000
R/W: R R/W R/W R/W R R R R/W