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16-Bit Timer Setup Examples
MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
95
Panasonic
TM4CA (example) x’00FE84’
3. Set the phase difference for timer 4. For a 2-cycle phase difference, write
x’0001’ to timer 4 compare/capture register B (TM4CB). (The valid range is
-1 ≤ TM4CB < the TM4CA value.)
TM4CB (example) x’00FE88’
4. Set the TM4NLD bit of the TM4MD register to 1 and the TM4EN bit to 0.
This enables TM4BC and the S-R flip-flop. This step ensures stable opera-
tion. If it is omitted, the binary counter may not count the first cycle. Do not
change any other operating modes during this step.
5. Set TM4NLD and TM4EN to 1. This starts the timer. Counting begins at the
start of the next cycle.
■
To enable timer 4 capture interrupts:
Cancel all existing interrupt requests. Next, set the interrupt priority level in the
TM4CBLV[2:0] bits of the TM4CBICH register (levels 0 to 6), set the TM4CBIE
bit to 1, set the TM4CBIR bit of TM4CBICL to 0, set the TM4CAIE bit of
TM4CAICH to 1, and set the TM4CAIR bit of TM4CAICL to 0. From this point
on, an interrupt request is generated whenever a timer 4 capture A or capture B
event occurs.
Timer 4 can operate as an event counter, but timer 4 does not operate in STOP
mode, when B
OSC
is off. If you use an external clock, it must be synchronized to
B
OSC
. This means that the frequency of the event counter clock must be 1/4 or
less that of the oscillator (6 MHz with a 24-MHz oscillator).
Figure 4-28 shows an example timing chart.
Bit:1514131211109876543210
TM4
CA15
TM4
CA14
TM4
CA13
TM4
CA12
TM4
CA11
TM4
CA10
TM4
CA9
TM4
CA8
TM4
CA7
TM4
CA6
TM4
CA5
TM4
CA4
TM4
CA3
TM4
CA2
TM4
CA1
TM4
CA0
Setting:0000000000000100
Bit:1514131211109876543210
TM4
CB15
TM4
CB14
TM4
CB13
TM4
CB12
TM4
CB11
TM4
CB10
TM4
CB9
TM4
CB8
TM4
CB7
TM4
CB6
TM4
CB5
TM4
CB4
TM4
CB3
TM4
CB2
TM4
CB1
TM4
CB0
Setting:0000000000000001
Figure 4-28 Event Counter Timing (Timer 4)
TM4CA
TM4CB
TM4BC
TM4IB
Interrupts
B
0000 0003 00000001
0004
0001
0002 0004 00030001 0002 0004
BA A