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H Counter
H Counter Control Registers
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
310
Panasonic
14.4 H Counter Control Registers
All registers in H Counter block cannot be written by byte (by word only). Read
by byte is possible.
HCCNT0: H Counter Control Register 0 x’007EB0’
SEDG0: Polarity select for count source signal (HI0)
0: Active low
1: Active high
SEDG0: Polarity select for reset signal
0: Active low
1: Active high
SELR20:00]: Reset signal select
000: 1024 µs
001: 2048 µs
010: 4096 µs
011: 8192 µs
100: VI0
101: VSYNC
All other settings default to 1024 µs.
HCCNT1: H Counter Control Register 1 x’007EB2’
SEDG1: Polarity select for count source signal (HI1)
0: Active low
1: Active high
SEDG1: Polarity select for reset signal
0: Active low
1: Active high
SELR[21:01]: Reset signal select
000: 1024 µs
001: 2048 µs
010: 4096 µs
011: 8192 µs
100: VI0
101: VSYNC
All other settings default to 1024 µs.
Bit:1514131211109876543210
———————————
SED
G0
RED
G0
SELR
20
SELR
10
SELR
00
Reset:0000000000000000
R/W:RRRRRRRRRRRR/WR/WR/WR/WR/W
Bit:1514131211109876543210
———————————
SED
G1
RED
G1
SELR
21
SELR
11
SELR
01
Reset:0000000000000000
R/W:RRRRRRRRRRRR/WR/WR/WR/WR/W