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Interrupts
Interrupt Control Registers
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
56
Panasonic
VBIICH: VBI (1) Interrupt Control Register (High) x’00FC67’
VBIICH enables VBI (1) interrupts. It is an 8-bit access register. Use the
MOVB instruction to access it.
The priority level for VBI (1) interrupts is written to the TM4CBLV[2:0]
field of the TM4CBICH register.
VBIIE: VBI (1) interrupt enable flag
0: Disable
1: Enable
TM5CBICL: Timer 5 Compare/Capture B Interrupt Control Register (Low) x’00FC68’
TM5CBICL detects and requests timer 5 compare/capture B interrupts. It
is an 8-bit access register. Use the MOVB instruction to access it.
TM5CBIR: Timer 5 compare/capture B interrupt request flag
0: No interrupt requested
1: Interrupt requested
TM5CBID: Timer 5 compare/capture B interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
TM5CBICH: Timer 5 Compare/Capture B Interrupt Control Register (High)x’00FC69’
TM5CBICH sets the priority level for and enables timer 5 compare/capture
B interrupts. It is an 8-bit access register. Use the MOVB instruction to
access it.
TM5CBLV[2:0]: Timer 5 compare/capture B interrupt priority level
Sets the priority from 0 to 6.
TM5CBIE: Timer 5 compare/capture B interrupt enable flag
0: Disable
1: Enable
Bit:76543210
———————
VBI
IE
Reset:00000000
R/W:RRRRRRRR/W
Bit:76543210
———
TM5CB
IR
———
TM5CB
ID
Reset:00000000
R/W:RRRR/WRRRR
Bit:76543210
—
TM5CB
LV 2
TM5CB
LV 1
TM5CB
LV 0
———
TM5CB
IE
Reset:00000000
R/W: R R/W R/W R/W R R R R/W