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IR Remote Signal Receiver Operation
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
222
Panasonic
8.3.6 Controlling the SLOW Mode
Use bit 7 (SP) in the RMLD reg-
ister to toggle the noise filter
sampling frequency between
PWM6/PWM8 and PWM3/
PWM5.
The MN102H series microcontrollers have two operating modes: NORMAL and
SLOW. (See section 3.1, “CPU Modes,” on page 72.) In SLOW mode, f
SYSCLK
= 2 MHz, which affects the frequencies of the PWM3 clock and noise filter
sampling (PWM6/PWM8). Use the SPSLW bit (bit 6) of the RMLD register to
change which clocks and noise filter sampling that you use.
Table 8-4 Differences between SLOW and NORMAL Modes
SPSLW
(RMLD,
bit 6)
Normal Mode
(f
SYSCLK
= 12 MHz)
SLOW Mode
(f
SYSCLK
= 2 MHz)
Noise filter sampling Clock Noise filter sampling Clock
0PWM6
(21.3 µs)
PWM8
(85.5 µs)
PWM3
(2.7 µs)
PWM6
(128 µs)
PWM8
(512 µs)
PWM3
(16 µs)
1PWM3
(2.7 µs)
PWM5
(10.7 µs)
PWM1
(0.67 µs)
PWM3
(16 µs)
PWM5
(64 µs)
PWM1
(4.0 µs)