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Interrupts
Interrupt Control Registers
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
60
Panasonic
TM1UDICH: Timer 1 Underflow Interrupt Control Register (High) x’00FC73’
TM1UDICH enables timer 1 underflow interrupts. It is an 8-bit access reg-
ister. Use the MOVB instruction to access it.
The priority level for timer 1 underflow interrupts is written to the
TM2UDLV[2:0] field of the TM2UDICH register.
TM1UDIE: Timer 1 underflow interrupt enable flag
0: Disable
1: Enable
TM0UDICL: Timer 0 Underflow Interrupt Control Register (Low) x’00FC74’
TM0UDICL register detects and requests timer 0 underflow interrupts. It is
an 8-bit access register. Use the MOVB instruction to access it.
TM0UDIR: Timer 0 underflow interrupt request flag
0: No interrupt requested
1: Interrupt requested
TM0UDID: Timer 0 underflow interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
TM0UDICH: Timer 0 Underflow Interrupt Control Register (High) x’00FC75’
TM0UDICH enables timer 0 underflow interrupts. It is an 8-bit access reg-
ister. Use the MOVB instruction to access it.
The priority level for timer 0 underflow is written to the TM2UDLV[2:0]
field of the TM2UDICH register.
TM0UDIE: Timer 0 underflow interrupt enable flag
0: Disable
1: Enable
Bit:76543210
———————
TM1UD
IE
Reset:00000000
R/W:RRRRRRRR/W
Bit:76543210
———
TM0UD
IR
———
TM0UD
ID
Reset:00000000
R/W:RRRR/WRRRR
Bit:76543210
———————
TM0UD
IE
Reset:00000000
R/W:RRRRRRRR/W