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Closed-Caption Decoder
Closed-Caption Decoder Registers
MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
239
Panasonic
HNUM: HSYNC Count Register x’007E06’
(HNUMW x’007E26’)
This register allows you to time the interrupt occurring after the line 21
data capture to a line other than line 21.
VBIIRQ[4:0]: VBI interrupt timing control
In this field, set the H line number, from 0 to 25, for the VBI interrupt. You
must set this field to x’13’ or higher.
SBFLAG: Start bit detection flag
0: No start bit detected
1: Start bit detected
HNUM[4:0]: HSYNC count during the VBI interval
This field indicates the H line number, from 0 to 25.
For designs using the closed-cap-
tion decoder, always tie the ACQ1
register to x’1312’.
ACQ1: ACQ Capture Timing Control Register 1 x’007E08’
(ACQ1W x’007E28’)
ACQ1E[4:0]: Stop position for ACQ capture 1
Valid range: x’00’ to x’25’
ACQ1S[4:0]: Start position for ACQ capture 1
Valid range: x’00’ to x’25’
CAPDATA: Caption Data Capture Register x’007E0A’
(CAPDATAW x’007E2A’)
CAPDA[15:0]: Caption data
This register stores the 16-bit captured caption data.
Bit:1514131211109876543210
———
VBI-
IRQ
4
VBI-
IRQ
3
VBI-
IRQ
2
VBI-
IRQ
1
VBI-
IRQ
0
SB
FLAG
——
HNU
M4
HNU
M3
HNU
M2
HNU
M1
HNU
M0
Reset:0001111100000000
R/W:RRRR/WR/WR/WR/WR/WRRRRRRRR
Bit:1514131211109876543210
———
ACQ1
E4
ACQ1
E3
ACQ1
E2
ACQ1
E1
ACQ1
E0
———
ACQ1
S4
ACQ1
S3
ACQ1
S2
ACQ1
S1
ACQ1
S0
Reset:0001111100011111
R/W: R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W
Bit:1514131211109876543210
CAP
DA15
CAP
DA14
CAP
DA13
CAP
DA12
CAP
DA11
CAP
DA10
CAP
DA9
CAP
DA8
CAP
DA7
CAP
DA6
CAP
DA5
CAP
DA4
CAP
DA3
CAP
DA2
CAP
DA1
CAP
DA0
Reset:0000000000000000
R/W:RRRRRRRRRRRRRRRR