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Closed-Caption Decoder
Closed-Caption Decoder Registers
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
244
Panasonic
Use this register to specify the position for capturing the pedestal level
value used during pedestal clamping. Specify a number of ADC clocks
after the leading edge of HSYNC. The valid range is x’000’ to x’1FF’, and
the recommended setting is x’003C’.
SYNCMIN: Sync and Pedestal Level Register x’007EC8’
(SYNCMINW x’007EE8’)
BPLV[6:0]: Pedestal level
This register stores the pedestal level captured from the position specified
in BPPST.
SYNCMIN[6:0]: Minimum sync level
This field stores the minimum level (the sync tip level) detected during the
interval set in the SCMING register. For sync tip clamping, you should
control clamping so as to make this value 16 (dec).
SPLV: Sync Separator Level Set Register x’007ECA’
(SPLVW x’007EEA’)
The sync separator uses the value set in this register to separate the com-
posite sync signal from the composite video signal.
Figure 9-13 Backporch Position Setting
Bit:1514131211109876543210
— BPLV6 BPLV5 BPLV4 BPLV3 BPLV2 BPLV1 BPLV0 —
SYNC
MIN6
SYNC
MIN5
SYNC
MIN4
SYNC
MIN3
SYNC
MIN2
SYNC
MIN1
SYNC
MIN0
Reset:0000000000000000
R/W:RRRRRRRRRRRRRRRR
Bit:1514131211109876543210
— — BSP5 BSP4 BSP3 BSP2 BSP1 BSP0 — — PSP5 PSP4 PSP3 PSP2 PSP1 PSP0
Reset:0001100000011000
R/W: R R R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W
Figure 9-14 Sync Separator Level
Pedestal level for BPLV register
Set this interval in BPPST
HSYNC
Video signal
Composite sync processing
Setting for sync
separator level
HSYNC
Video signal