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Interrupts
Interrupt Control Registers
MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
47
Panasonic
ADM3ICL
ADM3ICH
ADM2ICL
ADM2ICH
ADM1ICL
ADM1ICH
ADM0ICL
ADM0ICH
x’00FC78’
x’00FC79’
x’00FC7A’
x’00FC7B’
x’00FC7C’
x’00FC7D’
x’00FC7E’
x’00FC7F’
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address 3 match interrupt control register (low)
Address 3 match interrupt control register (high)
Address 2 match interrupt control register (low)
Address 2 match interrupt control register (high)
Address 1 match interrupt control register (low)
Address 1 match interrupt control register (high)
Address 0 match interrupt control register (low)
Address 0 match interrupt control register (high)
ANICL
ANICH
x’00FC80’
x’00FC81’
R/W
R/W
A/D conversion end interrupt control register (low)
A/D conversion end interrupt control register (high)
SCT0ICL
SCT0ICH
SCR0ICL
SCR0ICH
x’00FC82’
x’00FC83’
x’00FC84’
x’00FC85’
R/W
R/W
R/W
R/W
Serial 0 transmission end interrupt control register (low)
Serial 0 transmission end interrupt control register (high)
Serial 0 reception end interrupt control register (low)
Serial 0 reception end interrupt control register (high)
VBIVICL
VBIVICH
x’00FC88’
x’00FC89’
R/W
R/W
VBIVSYNC (1) interrupt control register (low)
VBIVSYNC (1) interrupt control register (high)
VBIVWICL
VBIVWICH
x’00FC8A’
x’00FC8B’
R/W
R/W
VBIVSYNC (2) interrupt control register (low)
VBIVSYNC (2) interrupt control register (high)
TM3UDICL
TM3UDICH
x’00FC8C’
x’00FC8D’
R/W
R/W
Timer 3 underflow interrupt control register (low)
Timer 3 underflow interrupt control register (high)
OSDGICL
OSDGICH
OSDCICL
OSDCICH
x’00FC90’
x’00FC91’
x’00FC92’
x’00FC93’
R/W
R/W
R/W
R/W
OSD (graphics) interrupt control register (low)
OSD (graphics) interrupt control register (high)
OSD (text) interrupt control register (low)
OSD (text) interrupt control register (high)
SCT1ICL
SCT1ICH
SCR1ICL
SCR1ICH
x’00FC98’
x’00FC99’
x’00FC9A’
x’00FC9B’
R/W
R/W
R/W
R/W
Serial 1 transmission end interrupt control register (low)
Serial 1 transmission end interrupt control register (high)
Serial 1 reception end interrupt control register (low)
Serial 1 reception end interrupt control register (high)
I2CICL
I2CICH
x’00FC9C’
x’00FC9D’
R/W
R/W
I
2
C interrupt control register (low)
I
2
C interrupt control register (high)
Note: The interrupt error interrupt control register does not exist in the hardware,
but if no matching interrupt vector is found for an interrupt that occurs, the
CPU writes a C to IAGR to indicate that it detected an abnormality.
Table 2-4 Interrupt Control Registers
Register Address R/W Description