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H Counter
H Counter Control Registers
MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
311
Panasonic
HCD0: H Counter Data Register 0 x’007EB4’
HCD[90:00]: Count from HI0 source signal
This field stores the HI0 clock source count. It becomes x’3FF’ on over-
flow.
HCD1: H Counter Data Register 1 x’007EB6’
HCD[91:01]: Count from HI1 source signal
This field stores the HI1 clock source count. It becomes x’3FF’ on over-
flow.
Bit:1514131211109876543210
——————
HCD
90
HCD
80
HCD
70
HCD
60
HCD
50
HCD
40
HCD
30
HCD
20
HCD
10
HCD
00
Reset:0000000000000000
R/W:RRRRRRRRRRRRRRRR
Bit:1514131211109876543210
——————
HCD
91
HCD
81
HCD
71
HCD
61
HCD
51
HCD
41
HCD
31
HCD
21
HCD
11
HCD
01
Reset:0000000000000000
R/W:RRRRRRRRRRRRRRRR