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Closed-Caption Decoder
Description
MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
227
Panasonic
9 Closed-Caption Decoder
9.1 Description
The MN102H75K/85K contains two identical closed-caption decoder circuits,
CCD0 and CCD1. The decoders extract encoded captions from composite video
signals. Figure 9-1 provides a block diagram of the decoders, and section 9.3,
“Functional Description,” on page 228, describes the circuit’s main blocks: the
analog-to-digital converter, clamping circuit, sync separator circuit, data slicer,
controller, and sampling circuit. Note that this section describes CCD0, but all
descriptions apply to CCD1. Table 9-1 provides the pin names for each decoder.
9.2 Block Diagram
Table 9-1 Pins Used for CCD0 and CCD1
Closed-Caption Decoder Pin Name
CCD0 CVBS0 VREFHS CLH0 CLL0
CCD1 CVBS1 VREFLS CLH0 CLL0
Figure 9-1 Closed-Caption Decoder Block Diagram
Clamp
ADC
Slicing
circuit
Max/min
detector
HSYNC separator
Clamping
controller
CRI
frequency
detector
Data extraction
controller
Data extractor
(sampling circuit)
VSYNC separator
S/P
RAM
CPU
CVBS
Data slicer
Sync separator
Low-pass filter
Slice level
detector
Controller