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Interrupts
Interrupt Control Registers
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
58
Panasonic
TM5UDICH: Timer 5 Underflow Interrupt Control Register (High) x’00FC6D’
TM5UDICH enables timer 5 underflow interrupts. It is an 8-bit access reg-
ister. Use the MOVB instruction to access it.
The priority level for timer 5 underflow interrupts is written to the
TM5CBLV[2:0] field of the TM5CBICH register.
TM5UDIE: Timer 5 underflow interrupt enable flag
0: Disable
1: Enable
VBIWICL: VBI (2) Interrupt Control Register (Low) x’00FC6E’
VBIWICL detects and requests VBI (2) interrupts. It is an 8-bit access reg-
ister. Use the MOVB instruction to access it.
VBIWIR: VBI (2) interrupt request flag
0: No interrupt requested
1: Interrupt requested
VBIWID: VBI (2) interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
VBIWICH: VBI (2) Interrupt Control Register (High) x’00FC6F’
VBIWICH register enables VBI (2) interrupts. It is an 8-bit access register.
Use the MOVB instruction to access it.
The priority level for VBI (2) interrupts is written to the TM5CBLV[2:0]
field of the TM5CBICH register.
VBIWIE: VBI (2) interrupt enable flag
0: Disable
1: Enable
Bit:76543210
———————
TM5UD
IE
Reset:00000000
R/W:RRRRRRRR/W
Bit:76543210
———
VBIW
IR
———
VBIW
ID
Reset:00000000
R/W:RRRR/WRRRR
Bit:76543210
———————
VBIW
IE
Reset:00000000
R/W:RRRRRRRR/W