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MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
31
Panasonic
1.6.2 MN102H75K Pin Description
Notes: 1. Pins marked with an asterisk (*) are N-channel, open-drain pins.
2. Pin 41 is V
DD
in the MN102H75K and V
PP
in the MN102HF75K.
Figure 1-10 MN102H75K Pin Configuration in Single-Chip Mode
84-Pin QFP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
NC
P71
P10, ADIN5, IRQ1
P11, ADIN6, IRQ2
P12, ADIN7, IRQ3
P72
P13, ADIN8, WDOUT
P14, ADIN9, STOP
P73
P15, ADIN10, PWM0
P16, ADIN11, PWM1
P17, PWM2
P20, PWM3
P21, PWM4
P22, PWM5
P23, PWM6
P24, TM4IC, SBT1
P25, TM4IOB, SBI1, SBD1
P26, TM4IOA, SBO1
P27, TM0IO
P74
P85
NC
P56, SBI0, SBD0
P57, SBT0
P60, SDA0 *
P86
P61, SCL0 *
VDD
OSC1
OSC2
VSS
P87
P00, RMIN, IRQ0
P01, SDA1 *
P02, SCL1 *
P03, ADIN0
P04, ADIN1
P05, ADIN2
P06, ADIN3
P07, ADIN4
P70
P80
P40, DAYMOUT, YM
P37, DABOUT, B
P77
P36, DAGOUT, G
P35, DAROUT, R
VREF, P34
P76
IREF
COMP
AVDD
P33, CLL
VREFLS
P32, CVBS1
NC
VSS
P31, CVBS0
VREFHS
P30, CLH
VDD (VPP)
P75
P55, SBO0
P54, IRQ5, VSYNC
P84
NC
P53, RST
P52, IRQ4, VI0
TEST
P51, YS
P83
P50, SYSCLK
P82
P47, HSYNC
P81
P46, OSDXI
P45, OSDXO
* P44, TM5IC, HI1
* P43, TM5IOB, HI0
* P42, TM5IOA
* P41, TM1IO
VCOI
PDO