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Data Integrity and Error Handling
6-4 Intel® 460GX Chipset Software Developer’s Manual
Note: In the SAC if there is a single-bit error and a double-bit error reported from the SDC on the same
cycle, then only the double-bit error is reported and only the double-bit error has its ITID captured
in the SAC. The SDC will have its SEC bit set and so software must read and clear all the errors in
the SDC after clearing the SAC.
A bit in FERR may be set that signals a minor error, such as correctable ECC error or other non-
fatal error. Another error may occur before FERR is serviced, thus forcing a bit in NERR to be set.
Since this next error may be fatal, both the FERR and NERR bits must be used to generate BINIT#,
BERR#, INTREQ# or whatever the appropriate action is.
Both the FERR and NERR registers are write-1-to-clear registers. This means that software must
write a one to the bits it wishes to clear.
For the GXB, all NERR and FERR registers must be cleared before FERR_GXB is cleared,
otherwise FERR_GXB will be set again.
6.4.1 Masked Bits
Many of the errors have conditional reporting behavior. The error always sets the FERR register or
NERR register. If the error is masked then a BINIT# or whatever is supposed to happen will not
occur, but the bit is still set. The mask will not prevent the error from appearing in FERR/NERR.
This allows software to poll, looking for errors that are not fatal to the system. If an error is
masked, it will still set FERR and force all other errors to appear in NERR, thus losing logging
information regarding later errors.
6.4.2 BERR#/BINIT# Generation
When an error occurs that forces BINIT#, then an enable bit in CONFIG2 is cleared as BINIT# is
driven to the bus. The enable bit is automatically cleared in order to mask further BINIT#
assertions. Software may also explicitly clear the enable bit to prevent BINIT# from occurring.
When an error occurs, software should go out, clean up the error, clear the error status registers and
only then set the enable bit so that new errors will be seen. When the bit is set, which can only be
done by software writing the bit, then the SAC will assert BINIT# on an error. If a new error occurs
after the first one is handled and is pending in FERR or NERR, then it will be reported when
software re-enables BINIT# reporting.
The same behavior is true for BERR# as well. It is enabled by a separate bit in CONFIG2.
6.4.3 INTREQ#
The INTREQ# signal is driven by the SAC when it wishes to cause an interrupt and signal the
operations system that an error has occurred that is non-fatal, but that may need to be logged. The
signal is held asserted as long as the condition that caused the error exists. All the errors that cause
an interrupt are OR-ed together to drive this signal. Software will reset the bit in FERR or NERR
that caused the error. When the bit is reset, INTREQ# should be deasserted unless there is another
error which holds the signal active.
After software clears the NERR/FERR bit that caused the error, it will do an EOI to the PID to re-
enable interrupt reporting by the PID. If INTREQ# is still active after the EOI, then a new interrupt
is generated.