Filter
Top Products
Intel® 460GX Chipset Software Developer’s Manual 6-13
Data Integrity and Error Handling
6.8.2 SAC Multiple Errors
There are several important cases of multiple errors in the SAC. Some of these are caused by the
SAC and SDC not being in one chip and therefore having delays in the handshaking paths that will
allow events that occur after a fatal problem to appear as errors, even when they are not real.
Some of the multiple errors and the behavior for the SAC are:
• If the system has a fatal error and there is a BINIT#, then the NERR register may contain
indications of other errors. For instance if there is a retirement from the SDC during the clock
the BINIT# is clearing the system bus queues, then a retirement underflow may be flagged.
6.8.3 Single Errors with Multiple Reporting
There are some cases where multiple error bits are set as data is passed along.
Data moving to the Expander bus from the SDC may cause multiple error bits to be set. For
instance, there is a PCI read that gets a system bus or memory ECC error. The SDC will flag the
error and the expander unit will also flag that the error occurred. Either may come in first, so that
FERR may have the expander bus error and NERR have SDC system bus error, or vice-versa.
A second case is for data from the expander bus to memory. The data is poisoned across the private
data bus. Therefore FERR_SAC will be set for an expander bus parity error, and NERR_SAC will
be set for a SNE error from the SDC.
The GXB may have an address from the graphics card that is in the aperture range, but finds the
Valid bit cleared in the GART entry. This will set FERR_GART[2]. Since the address won’t be
translated, it is likely to be outside a valid memory range, thus an Illegal Address error is likely.
Since this is one operation, both bits 2 and 1 of FERR_GART are set.
Data in the SDC is handled on an 8-byte basis, so that poisoned data causes 8 bytes to have bad
parity. The expander interface in the SAC handles the data on a 4-byte basis. Therefore a single
8B data transfer that is on an 8B aligned address will cause both the FERR and NERR bits to be
set, because each 4B is flagged as a separate error. If the access starts on an odd 4B boundary, then
only the FERR register is set, since only 4 bytes are accessed out of the bad 8 bytes.
6.8.4 Error Anomalies
There are several cases that may have unexpected behavior. These are listed below.
Assume there is a 2x error in a certain 8B chunk of DRAM. There is a partial write which writes
all 8 bytes of the bad chunk. One might expect that, since the partial write overwrote all 8 bytes of
the chunk, the error would not be reported. The GX design is such that the data buffer in the SDC
tracks errors on 8B chunks. The data is marked as having a 2x error when the line is read out of
DRAM. Even though the entire 8B is overwritten, the chunk is still marked as having a 2x error.
When the line with the merged data is written back into DRAM, the chunk that has the 2x error will
be poisoned and later reads will report a 2x error on that line. NOTE: if there is a full line write,
then any line in DRAM with a 2x ECC error will be overwritten, and the 2x error will never be
seen.
An expander bus MWI writes an entire line into DRAM. On the system bus there is an implicit
writeback. The data from the processor for the IWB has a 2x error. Even though the processor data
is not used, since the expander bustransaction was a full line write, the data will be sent to DRAM
as poisoned.