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Register Descriptions
2-36 Intel® 460GX Chipset Software Developer’s Manual
2.5.3 PXB
2.5.3.1 PMD[1:0]: Performance Monitoring Data Register
Address Offset: D8-DBh, E0-E3h Size: 32 bits each
Default Value: 0000_0000h each Attribute: Read/Write
Two performance monitoring counters, with associated event selection and control registers, are
provided for each PCI bus in the PXB. Each counter may be configured to track PCI bus events.
Event detection may be configured to increment a counter, toggle a pin on event or counter
overflow, and issue an interrupt request on counter overflow.
The PMD registers hold the performance monitoring count values. These registers are 32-bit
counters. Event selection is controlled by the PME registers, and the action performed on event
detection is controlled by the PMR registers.
Each counter may be stopped/started independently, using the controls available in the associated
PMR register.
Bits
Description
31:0 Count Value
2.5.3.2 PMR[1:0]: Performance Monitoring Response
Address Offset: DDh, E5h Size: 8 bits each
Default Value: 0000h each Attribute: Read/Write
There are two PMR registers for each PCI bus, one for each PMD counter. Each PMR register
specifies how the event selected by the corresponding PME register affects the associated PMD
register, P(A,B)MON# pins, and the INT(A,B)RQ# pins.
Bits
Description
7:6 Interrupt Assertion
Defines how selected event affects INTRQ# assertion. Whenever INTRQ# is asserted, a
flag for this counter is set in the Error Status Register, so that software can determine the
cause of the interrupt. This flag is reset by writing the Error Status Register.
5:4 Performance Monitoring pin assertion
Defines how the selected event affects the PMON# pin for this counter.
3:2 Count Mode
Selects when the counter is updated for the detected event.
0 Selected event does not assert INTRQ #
1 reserved
2Assert INTRQ# pin when event occurs
3Assert INTRQ# pin when counter overflows
0 PMON# pin is tristated. Selected event has no effect.
1 reserved
2 Assert this counter’s PMON# pin when event occurs
3 Assert this counter’s PMON# pin when counter overflows
0 Stop counting.
1 Count each cycle selected event is active.
2 Count on each rising edge of the selected event.
3 Trigger. Start counting on the first rising edge of the selected event, and
continue counting each clock cycle.