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LPC/FWH Interface Configuration
11-20 Intel® 460GX Chipset Software Developer’s Manual
11.2.1.11 Dmc–Dma Master Clear Register (I/O)
I/O Address: Channel 0-3–00Dh; Channel 4-7–0DAh
Default Value: All bits undefined
Attribute: Write Only
This software instruction has the same effect as the hardware Reset.
11.2.1.12 Dclm–Dma Clear Mask Register (I/O)
I/O Address: Channel 0-3–00Eh; Channel 4-7–0DCh
Default Value: All bits undefined
Attribute: Write Only
This command clears the mask bits of all four channels, enabling them to accept DMA requests.
11.2.2 Interrupt Controller Registers
The IFB contains an interrupt controller that incorporates the Functionality of two 82C59 interrupt
controllers. The interrupt registers control the operation of the interrupt controller.
11.2.2.1 Icw1–Initialization Command Word 1 Register (I/O)
I/O Address: INT CNTRL-1–020h; INT CNTRL-2–0A0h
Default Value: All bits undefined
Attribute: Write Only
A write to Initialization Command Word 1 starts the interrupt controller initialization sequence.
Addresses 020h and 0A0h are referred to as the base addresses of CNTRL-1 and CNTRL-2,
respectively. An I/O write to the CNTRL-1 or CNTRL-2 base address with bit 4 equal to 1 is
interpreted as ICW1. For IFB-based systems, three I/O writes to “base address + 1" must follow the
ICW1. The first write to “base address + 1" performs ICW2, the second write performs ICW3, and
the third write performs ICW4.
ICW1 starts the initialization sequence during which the following automatically occur:
1. The Interrupt Mask register is cleared.
2. IRQ7 input is assigned priority 7.
3. The slave mode address is set to 7.
4. Special Mask Mode is cleared and Status Read is set to IRR.
Bit Description
7:0 Clear Byte Pointer. No specific pattern. Command enabled with a write to the I/O port
address.
Bit Description
7:0 Master Clear. No specific pattern. Command enabled with a write to the I/O port address
Bit Description
7:0 Clear Mask Register. No specific pattern. Command enabled with a write to the I/O port
address.