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PCI/LPC Bridge Description
15-2 Intel® 460GX Chipset Software Developer’s Manual
internal interrupts are used for internal Functions only. IRQ2 is used to cascade the two controllers
together and is not available to the user. IRQ0 is used as a system timer interrupt and is tied to
Interval Timer 1, Counter 0. IRQ13 is connected internally to FERR#. The remaining 13 interrupt
lines (IRQ1, IRQ3-IRQ12, IRQ14, and IRQ15) are available for external system interrupts. Edge
or level sense selection is programmable on an individual channel by channel basis, except for
IRQ0, IRQ2, IRQ8#, and IRQ13.
The Interrupt unit also supports interrupt steering. The IFB can be programmed to allow the four
PCI active low interrupts (PIRQA#-PIRQD#) to be internally routed to one of 11 interrupts: 3 - 7,
9-12, 14 or 15.
The Interrupt Controller consists of two separate 82C59 cores. Interrupt Controller 1 (CNTRL-1)
and Interrupt Controller 2 (CNTRL-2) are initialized separately and can be programmed to operate
in different modes. The default settings are: IA-32 Compatibility Mode, Edge Sensitive (IRQ0-15)
Detection, Normal EOI, Non-Buffered Mode, Special Fully Nested Mode disabled, and Cascade
Mode. CNTRL-1 is connected as the Master Interrupt Controller and CNTRL-2 is connected as the
Slave Interrupt Controller.
Note that IRQ13 is generated internally (as part of the coprocessor error support) by the IFB.
15.2.1 Programming the Interrupt Controller
The Interrupt Controller accepts two types of command words generated by the CPU or bus
master:
15.2.1.1 Initialization Command Words (ICWs)
Before normal operation can begin, each Interrupt Controller in the system must be initialized. In
the 82C59, this is a two to four byte sequence. However, for the IFB, each controller must be
initialized with a four byte sequence. This four byte sequence is required to configure the interrupt
controller correctly for the IFB implementation.
The four initialization command words are referred to by their acronyms: ICW1, ICW2, ICW3, and
ICW4.
The base address for each interrupt controller is a fixed location in the I/O memory space, at 0020h
for CNTRL-1 and at 00A0h for CNTRL-2.
An I/O write to the CNTRL-1 or CNTRL-2 base address with data bit 4 equal to 1 is interpreted as
ICW1. For IFB-based systems, three I/O writes to “base address + 1" (021h for CNTRL-1 and
0A1h for CNTRL-2) must follow the ICW1. The first write to “base address + 1” (021h/0A1h)
performs ICW2, the second write performs ICW3, and the third write performs ICW4.
ICW1 starts the initialization sequence.
ICW2 is programmed to provide bits [7:3] of the interrupt vector that will be released onto the data
bus by the interrupt controller during an interrupt acknowledge. A different base [7:3] is selected
for each interrupt controller.
ICW3 is programmed differently for CNTRL-1 and CNTRL-2, and has a different meaning for
each controller.
For CNTRL-1, the master controller, ICW3 is used to indicate which IRQx input line is used to
cascade CNTRL-2, the slave controller. Within the IFB interrupt unit, IRQ2 on CNTRL-1 is used
to cascade the INTR output of CNTRL-2. Consequently, bit-2 of ICW3 on CNTRL-1 is set to a 1,
and the other bits are set to 0's.