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System Architecture
3-6 Intel® 460GX Chipset Software Developer’s Manual
location, there is no guarantee that AGP has not written the location while the lock was active on
the system bus. AGP may read or write those locations or any other memory location, independent
of the processor lock.
3.7 Interrupt Delivery
Interrupts may be delivered to the processors over the system bus. The interrupts may come from
an I/O device or from another processor. The new system bus delivery method for interrupts to
Itanium processor is referred to as SAPIC.
For SAPIC, the interrupts appear on the bus with a specific encoding on the REQa/REQb signals.
The address used is 0x000FEEzzzzy. The 16 bits ZZZZ determine the target to which the interrupt
is being sent. Both I/O interrupts and inter-processor interrupts are delivered in this manner. The
data field contains the interrupt vector.
Devices may send their interrupts to one specific processor, or have the system choose the
processor to which to deliver the interrupt. The algorithm used by the system to deliver interrupts
depends on the software. The chipset will have a register for each processor. This register, called
the XTPR (eXternal Task Priority Register), is programmable and may be set as software wishes.
One could use this feature for lowest-priority delivery, as one example. The processor updates its
XTPR when it updates its own internal priority register. An interrupt which is received by the
chipset with the redirectable hint bit set, will be sent to the processor with the lowest value in the
XTPR. If 2 or more processors tie for the lowest value, the processor with the lowest processor ID
will be selected.
The 4 XTPR registers in the 460GX chipset are updated when the processor does a special cycle on
the bus. When the special cycle is decoded, the low order 3 bits of the DID are used to determine
which register to update. Each XTPR register is disabled at reset, and requires a special cycle
XPTR-update to be enabled.
3.8 WXB PCI Hot-Plug Support
“Hot-Plug” is the term given to describe the capability to insert and remove PCI add-in cards into a
computer while the PCI bus itself and other subsystems in the computer are fully operational. Hot-
Plug logic in the WXB supports system hot-plug capability by providing the state machines and
programming interface to individually power up and power down PCI slots in a controlled fashion.
An Integrated Hot-Plug Controller (IHPC) comprises the hot-plug logic for one PCI bus.
Hot-Plug functionality in a complete system which includes the WXB requires three subsystems to
work together: (1) the software subsystem, including firmware and drivers, (2) the hardware logic
subsystem in the WXB, including hot-plug registers and memory and state machines, and (3) the
external hardware subsystem, including interlock switches, shift registers, FETs, and LEDs on each
PCI bus.
The PCI hot-plug logic performs three sets of operations: reset, slot enable (power-up and connect
to bus), and slot disable (disconnect from bus and power-down). In normal operation, slot enable
and slot disable occur only under software direction. Slot disable may occur automatically if a PCI
card generates a power fault or if the user opens an interlock switch to remove a powered-up PCI
card. The slot enable and disable sequences are briefly described below.