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Intel® 460GX Chipset Software Developer’s Manual 2-39
Register Descriptions
38:0 Count Value
This register contains the Performance Monitor Data Register. You may preset the value
of the performance counter by writing to this register. You may read back the value of the
performance counter by reading this register.
2.5.4.2 PCI_PMD: PCI Performance Monitor Data Registers
Function Number: BFN+1
Address Offset: 60h Size: 64 bits
Default Value: 0 Attribute: Read/Write
Sticky: No Locked: No
This counter may be configured to track PCI bus events as well as events internal to the GXB.
Event detection may be configured to increment a counter, affect performance monitoring pins, and
issue an interrupt request on counter overflow.
The value written to this address, loads the counter and is also saved in a reload register. Each
counter can be configured to reload the data.
The PCI_PMD register holds the performance monitoring count value. 39-bits of the counter are
used for event counting, the 40th-bit is used as a overflow detection bit. The 39-bit count value
allows up to 70 minutes of event collection at 133 MHz. Event selection is controlled by the PMC
registers.
Each counter may be stopped/started independently, using the controls available in the associated
PMD register.
Bits
Description
63:40 reserved(0)
39 Overflow
This bit is asserted when the Event Count bit 38 carries into bit 39.
38:0 Count Value
This register contains the Performance Monitor Data Register. You may preset the value
of the performance counter by writing to this register. You may read back the value of the
performance counter by reading this register.
2.5.4.3 PERCON: Performance Monitor Control Register
Function Number: BFN+1
Address Offset: E0h Size: 8 bits
Default Value: 00h Attribute: Read/Write
Sticky: No Locked: No
The PERCON Register allows one software write to start and stop the performance monitors. The 2
bits are fed into the Event Logic generation. Bit 0 feeds Event 0 and bit 1 feeds Event 1. Since the
counters can be enabled and disabled by Events 0 or 1, then one write can start or stop all the
counters together.
Bits
Description
7:2 reserved (0)
1 Event 1 Input
This bit is fed as an input into Event 1 logic. This bit is OR’ed with any other logic
generating Event 1, guaranteeing that if this bit is set, then Event 1 will be asserted.