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Intel® 460GX Chipset Software Developer’s Manual 7-1
AGP Subsystem 7
AGP is a new port defined for graphics adapters. In the initial implementation it is a 500 MB/s port.
There is also an extension called AGP 4X mode, which has a bandwidth of 1 GB/s. AGP 2X mode
cards will work in an AGP 4X mode slot. The 460GX chipset is designed to work at the AGP 4X
mode bandwidths. It will support 3.3V AGP 1X and 2X mode cards as well.
AGP 4X mode is a high-bandwidth port targeted to workstation graphics needs. It provides 1 GB of
data bandwidth. There are several protocol modes. One mode is 66 MHz PCI. The other mode is
the new AGP protocol, which comes in two flavors. The first is an extension of PCI using PIPE#
instead of FRAME#. The second uses sideband signals to improve bandwidth. Only one AGP
protocol may be in effect at a time. Both of the modes using AGP protocol and the mode using PCI
protocol are fully supported.
This chapter explains the 460GX chipset implementation of AGP and related issues. It assumes
that the reader is familiar with the AGP and AGP 4X mode specifications. This chapter explains
the GX implementation of the AGP interface to the GXB and the interface between the GXB and
the rest of the chipset, which is the expansion bridge chip containing the AGP port. It will not
explain AGP protocol or the AGP bus itself.
7.1 Graphics Address Relocation Table (GART)
Graphics cards, especially for texture traffic, would like to see a large contiguous view of memory.
This allows them to make random accesses into a large area which contains the entire texture map
for the displayed image. Processors have the same view of a flat contiguous memory range in their
virtual space, where a program may have many megabytes of contiguous address space to use. The
memory pointed to by those virtual addresses will most likely be discontiguous in main memory.
The processor, through page tables and TLBs, remaps the contiguous virtual addresses to the
discontiguous physical DRAM addresses. For graphics cards, the chipset will perform the same
translation. The graphics card uses, in essence, a virtual address. This address is translated by the
chipset’s Graphics Address Relocation Table (GART) from the virtual address used by the graphics
card to the physical DRAM address the memory controller understands.
The GART table is loaded by the graphics device driver at initialization time. The table resides in
the GXB, so that translations will be fast and not interfere with main memory traffic. The table will
contain a new page address for each address coming in from the graphics card. It will also contain
a bit to determine whether addresses to that page need to be snooped on the system bus or not. The
following figures show how the GART operates. There is a base address for AGP addresses and a
length for the AGP range. Addresses are received from the graphics card. If the address is in the
AGP range, the page number within that range is used as a pointer into the GART and a new page
address is combined with the 12 (22 for 4 MB pages) least significant bits of the address from the
graphics card. This new address is used by the memory system. If the address doesn’t hit inside the
AGP-space, then no translation is done. Note that the AGP_BASE address bits 27:12 are always a
0 (hardwired in config register).