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Intel® 460GX Chipset Software Developer’s Manual 2-31
Register Descriptions
The IT_MON_PMD_[0 to 5] registers hold the performance monitoring count values. 39-bits of
the counter are used for event counting, the 40th-bit is used as a overflow detection bit. The 39-bit
count value allows up to 70 minutes of event collection at 133 MHz. Event selection is controlled
by the PMC registers (Section 2.5.1.2).
Each counter may be stopped/started independently, using the controls available in the associated
PMC register.
Bits
Description
63:40 reserved(0)
39 Overflow
This bit is asserted when the Event Count bit 38 carries into bit 39.
38:0 Count Value
This register contains the Performance Monitor Data Register. You may preset the value
of the performance counter by writing to this register. You may read back the value of the
performance counter by reading this register.
2.5.1.2 IT_MON_PMC_[0 to 5]: Internal Transaction Performance Monitor
Config. Register
Bus CBN, Device Number: 00h Function: 2
Address Offset: D0-D7h, D8-DFh, Size: 64 bits each
E0-E7h, E8-EFh,
F0-F7h, F8-FFh
Default Value: 0h each Attribute: Read/Write
Sticky: No Locked: No
The IT_MON_PMC_[0 to 5] Registers specify the configuration of the Internal Transaction
Performance Monitors. This includes specifying Event Selection, Unit Mask, Enable & Disable
Source and Reload Control.
Bits
Description
63:41 reserved(0)
40:33 Length Encodings
0000 0000b Any Length Transaction
0111 0000b 0 - 8 Bytes
0111 0001b 16 Bytes
0111 0010b 32 Bytes
0111 0111b 48 Bytes
0111 0011b 64 Bytes
0110 0000b < 32 Bytes
1000 0011b < 64 Bytes
Note: Length Encodings only used during the following Performance Monitor Setting:
Mem Read - Delayed
Mem Read - Deferred Reply
Memory Write
32:24 DMASK Encodings
0 0001 1010 - Configuration Space - Monitor transactions Destined for Config Block
0 0000 1100 - Memory - Monitor transactions Destined for Memory
0 0001 1110 - Broadcasts - Monitor Broadcasts
1 0000 0000 - All Destinations - Monitor all Destinations