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Intel® 460GX Chipset Software Developer’s Manual 10-17
IFB Usage Considerations
II. Provide recovery for data transfers that fail as the result of Ultra DMA/33 Interface CRC
Errors:
A. Determine that the data transfer command’s error source is Ultra DMA/33 Interface CRC
error.
B. Retry data transfer command when Ultra DMA/33 Interface CRC is the source of error.
III. Ensure that the Ultra DMA/33 configuration of the devices and host controller is restored
when events that clear the Ultra DMA/33 enabled status are encountered.
• Ensure that Hard Resets are never issued to the device during a power cycle -OR-
• Provide path to Ultra DMA/33 Aware firmware and/or System Initialization Software in
the case of a Hard/Power-On reset.
When enabled on the host controller and devices, Ultra DMA/33 operation shall be used for all data
transfer commands issued by the Ultra DMA/33 Aware Device Driver with PCI Bus Master IDE,
DMA operation. PIO or Multi Word DMA shall be the mode of access used with devices and host
controllers that do not support Ultra DMA/33.
10.5.11 Additional Ultra DMA/PCI Bus Master IDE Device Driver
Considerations
This section provides information regarding Terminating Transfers performed with Ultra DMA/
PCI Bus Master IDE device drivers or system software.
In normal bus master operations, at the end of a data transfer, the IDE device signals an interrupt.
In response to the interrupt, software verifies that the bus is idle and then writes the Stop Bus
Master Command. It then reads the controller status register to determine if the transfer completed
successfully. For a detailed description of the Bus Master IDE Status Register refer to the last
section of this document called Bus Master IDE Command and Status Registers.
If the IDE device does not signal the interrupt, the last bus master transfer did not complete. In this
case, it is necessary to read the Bus Master IDE Status Register to check if the bus is idle or active.
If the bus is active it is necessary to send the Stop Bus Master Command and reset the IDE
controller and drives connected to the IDE cable prior to sending out the next ATA/ATAPI drive
command to the cable. This is necessary because the cable (Primary or Secondary IDE) may not be
ready to receive new commands unless the Bus Master state machine has stopped. All the drives on
the cable should be reset.
In general, a prematurely terminated command on the IDE bus implies that some of the state
machines in the drive and/or in the IFB are still in an “active” condition. By performing a drive
reset immediately following the burst “stop”, the IFB will be in a state such that the IDE DMA
engines can be programmed to perform the transfer once again.
10.5.11.1 Bus Master IDE Command and Status Register
10.5.11.2 BMICX–Bus Master IDE Command Register (I/O)
Address Offset: Primary Channel–Base + 00h; Secondary Channel–Base + 08h
Default Value: 00h
Attribute: Read/Write