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Intel® 460GX Chipset Software Developer’s Manual 2-29
Register Descriptions
each of these errors varies and is (generally) controlled through a combination of the PCICMD and
ERRCMD registers. Refer to Section 6.12 for information on the conditional reporting of these
errors via the SERR#, XBINIT#, or INTRQ# outputs.
Note, if multiple errors are observed very close in time multiple errors may be signaled as a first
error.
Bits
Description
7 PCILV: PCI Error Logs Valid
This flag is set when an error has been logged in the FEPCIAL and FEPCIDL log
registers. The FEPCI status bit that lead to the logging must be cleared prior to clearing
the PCILV flag. Default = 0.
6 UMATA: Unexpected Master or Target Abort
This flag is set when an unexpected master abort or any target abort occurs. Master
aborts are reported as described for the RMA bit in the PCISTS register. Target aborts
through the RTA bit. Default = 0.
5 DTE: Discard Timer Expiration
This flag is set when the 2
15
clock timeout timer expires. This flag may be configured to
assert SERR#, XBINIT#, or an INTRQ interrupt through the ERRCMD register.
Default = 0.
4 SES: System Error Signaled
This flag is set when the a PCI agent other than the WXB asserts SERR#. This flag may
be configured to assert XBINIT#, or an INTRQ interrupt through the ERRCMD
register. Default = 0
3 PODT: PERR# Observed on PCI Data Transfer
This flag is set if the WXB detects the PERR# input asserted, and the WXB was not the
asserting agent. This flag may be configured to assert SERR#, XBINIT#, or an INTRQ
interrupt through the ERRCMD register. Default = 0.
2 reserved (0)
1 PEOD: Parity Error on Received PCI Data
This flag is set if the WXB detects an parity error (i.e. calculates a parity different from
what is provided with the data) on data being sent to the WXB on the PCI bus (from a
master read or target write). Default = 0.
0 PEPA: Parity Error on PCI Address
This flag is set if the WXB detects a parity error on the PCI address. Default = 0.
2.4.6.4 NEPCI: PCI Bus Next Error Status Register
Address Offset: 87h Size: 8 bits
Default Value: 00h Attribute: Read/Write Clear,
Sticky
This register records any PCI bus errors detected after the first error is observed and recorded in the
FEPCI register. This register is a write-1-to-clear register, meaning that software must write a 1 to
the specific bit location it wishes cleared. The response to each of these errors varies and is
(generally) controlled through a combination of the PCICMD and ERRCMD registers. Error
logging is not performed for Next Error occurrences.
Bits
Description
7:0 See the FEPCI register description for definitions. Error logging is not performed for
Next Error occurrences.