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Intel® 460GX Chipset Software Developer’s Manual 2-33
Register Descriptions
001 0111b Memory Read that was to be retried and received a HITM
001 1000b Memory Read with active OWN# and received a HITM
001 1001b Memory Read from a CPU that received a HITW
001 1010b Memory Read from a CPU that received a HITM
001 1011b Memory Read from PCI that received a HITW
001 1100b Memory Read from PCI that received a HITM
001 1101b Memory Write from PCI that received a HITM
010 0001b EV0 Events
010 0010b EV0 Clocks
010 0011b EV1 Events
010 0100b EV1 Clocks
7 reserved(0).
6:5 Disable Source
Selects event that will disable the performance monitor.
00b Never Disable.
01b Disable when this counter is overflowed (Note that if this setting is used, and bits
[4:3] are set to ’Enable Always’, then when this counter is overflowed, counting
will not resume until the counter is loaded with a non-overflow value).
10b Disable on falling edge of SAC Event 0.
11b Disable on falling edge of SAC Event 1.
4:3 Enable Source
Selects event that will enable the performance monitor.
00b Never Enable.
01b Enable Always (Disable events overrides this setting and will disable counting).
10b Enable on rising edge of SAC Event 0.
11b Enable on rising edge of SAC Event 1.
2:0 Reload Control
Selects event that will control the Reloading of the performance monitor with the value
written into the associated PMD2 register.
000b Never Reload.
001b Reload when counter overflows.
010b Reload on SAC Event 0 Asserted.
011b Reload on SAC Event 1 Asserted.
100b Reload on SAC Event 0 Asserting edge.
101b Reload on SAC Event 1 Asserting edge.
Note: When counting retried reads (code of 110_0110b) the logic will count reads that were to be retried,
but got a HITM# and therefore the HITM# overrides the retry. For an exact count of reads that are
truly retried, count retried reads (110_0110b) and subtract out the number of reads that were to be
retried but got a HITM# (code of 001_0111b). This give the exact number of reads that were retried
on the bus.