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Intel® 460GX Chipset Software Developer’s Manual 7-5
AGP Subsystem
7.1.3 GART Implementation
Figure 7-5 shows the timings for the SRAM interface. Synchronous SRAM will be clocked at 7.5
ns. The SRAM will be used in the pipelined mode. This allows addresses to be presented to the
SRAM every cycle. The data is valid to be latched by the GXB on the 3rd clock edge after the
clock edge which drove the address. Writes require the data to be driven with the address. The
entire 32 bits of data are read or written at one time.
NOTES:
1. LBO# is a don’t care, but must be tied either high or low.
2. SE1#, SE2, ADSC#, ADSP#, ADV#, LBO#, SB# and SW# are not connected to the GXB.
These signals must be tied to the required level by the board.
7.1.4 Coherency
Traffic from the graphics card may or may not want to be coherent with the system bus. For the
discussion here, coherency means that addresses will appear on the system bus so that the
processors may snoop their caches for that address. If the texture map or other image data is
marked WC by the processor, then that data is not coherent. Addresses on the bus which hit in a
processor’s WC buffer are not snooped and even if there is dirty data in the buffer, no implicit
writeback is done. Or the application may know that the data in memory was not used by the
processor (e.g. it came from disk) and wants the graphics card to fetch the data without using
address bus bandwidth, so forces the access to be non-coherent.
Figure 7-5. GART SRAM Timings
1 2 3 4 5 6 7 8 910111213141516
Rd1 Rd2 Rd3 Rd4 WrA WrB WrC
Q(1) Q(2) Q(3) Q(4) D(A) D(B) D(C)
WrD
D(D)
0ns 25ns 50ns 75ns 100ns
K
SA(17:0)
SE3#
SGW#
G#
DQ(31:0)
SE1#
SE2
ADSC#
ADSP#
ADV#
LBO#
SB#
SW#