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WXB Hot-Plug
8-12 Intel® 460GX Chipset Software Developer’s Manual
8.2.1 Page Number List for IHPC Memory Mapped Register
Descriptions
Register Page
Extended Hot-Plug Miscellaneous................................................................8-18
LED Control..................................................................................................8-13
General Purpose Output................................................................................8-17
Hot-Plug Interrupt and Clear.........................................................................8-14
Hot-Plug Interrupt Mask...............................................................................8-15
Hot-Plug Miscellaneous................................................................................8-13
Hot-Plug Non-interrupt Inputs......................................................................8-17
Hot-Plug Slot Identifier.................................................................................8-17
Hot-Plug Switch Interrupt Redirect Enable..................................................8-18
Serial Input Byte Data...................................................................................8-16
Serial Input Byte Pointer...............................................................................8-17
Slot Enable....................................................................................................8-12
Slot Power Control........................................................................................8-18
8.2.2 Slot Enable
Address Offset: 01h Size: 8 bits
Default Value: 00h Attribute: Partial Read/Write (Pwr Good Rst Only)
Used to power-on a slot and connect it to the bus (or disconnect and power-down). The SOGO bit
must be set to start the output sequence. The set of usable Enable Slot bits is determined by the
strapping values on the P(A,B)HSIL, P(A,B)HSOL, and P(A,B)HSOC inputs. Unsupported slots in
a system do not have writeable Enable Slot bits. Writing a zero to a Enable Slot bit will clear the
associated Slot Power register bit.
Bits
Description
7:6 reserved(0)
5 Enable Slot F
When 1, Slot F is powered and connected to the PCI bus
4 Enable Slot E
When 1, Slot E is powered and connected to the PCI bus
3 Enable Slot D
When 1, Slot D is powered and connected to the PCI bus
2 Enable Slot C
When 1, Slot C is powered and connected to the PCI bus
1 Enable Slot B
When 1, Slot B is powered and connected to the PCI bus
0 Enable Slot A
When 1, Slot A is powered and connected to the PCI bus