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Intel® 460GX Chipset Software Developer’s Manual 4-3
System Address Map
4.1.2 Low Extended Memory Region
The 15 MB Low Extended Memory region is always mapped to main memory. Since the 460GX
chipset does not support ISA cards, there is no gap provided in this region.
4.1.3 Medium Extended Memory Region
The Medium Extended Memory region is divided into two primary regions: A fixed gap containing
the firmware area along with gaps for Itanium processor and chipset specific functions, and a
variable gap to support memory mapped I/O.
The fixed gap is between 4 GB and (4 GB minus 32 MB) and is always enabled. This region must
not be defined as WB. DRAM supported by the 460GX chipset that is masked by this hole is
remapped to an area over 4 GB. The fixed gap is further divided into three regions:
• The 4 GB to (4 GB minus 16 MB) region is reserved for system firmware. Addresses directed
to this area are always directed to the compatibility PCI bus.
• The (4 GB minus 16 MB) to (4 GB minus 20 MB) region is reserved for processor specific
functions. This region can be thought of as four 1 MB segments:
— FEF0_0000 - FEFF_FFFF: This segment is used for Local APIC messages. Neither
inbound nor outbound accesses to this region should be seen by the chipset. The chipset
claims outbound accesses to this region, and will forward reads to PCI 0a to be master
aborted and drops the writes. Inbound accesses to this region can only occur due to a
programming error or address parity error; firmware programs the Expander bridges to
prevent programming errors from reaching the SAC; address parity errors are protected
against at each of the major bus interfaces. Therefore the SAC does not require a defined
response for inbound requests that reach this area; the results are unpredictable.
— FEE0_0000 - FEEF_FFFF: This segment is used to deliver interrupts. The chipset claims
outbound accesses to this region, and will forward reads to PCI 0a to be master aborted
and drops the writes. Inbound writes to this region are translated to an interrupt command
encoding, forwarded to the system bus, and then claimed by the chipset. Reads to this area
are illegal.
— FED0_0000 - FEDF_FFFF: This segment is reserved. The chipset claims outbound
accesses to this region, and will forward reads to PCI 0a to be master aborted and drops
the writes. Inbound accesses to this region are illegal.
— FEC0_0000 - FECF_FFFF: This segment is used for SAPIC messages. The chipset claims
outbound accesses to this region and forward them to the appropriate PCI bus. The
processors use this region to program the SAPIC or IOAPIC registers and for targeted
EOI writes. Inbound accesses to this region are illegal.
• The (4G minus 20M) to (4G minus 32M) region is reserved for chipset specific functions.
Inbound accesses to this region are expected only from the compatibility PCI bus from either a
server management or a validation card. IB accesses are directed to the system bus and then
forwarded to the appropriate PCI segment. This region is segmented as follows (unlisted
regions are reserved):
— FE20_0000 - FE3F_FFFF: This range is for programming the GART. Reads and writes
are sent to Expander port-2 to be forwarded to the GXB. If the DEVNPRES bit for Device
14 is set (meaning that there is no xXB attached to the Expander bus), then accesses to this
region will be forwarded to the compatibility bus for termination.
— FEB0_0CB0: This address is for a memory-mapped register in the SAC.