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Intel® 460GX Chipset Software Developer’s Manual 8-5
WXB Hot-Plug
8.1.5 PCISTS: PCI Status Register
Address Offset: 06h – 07h Size: 16 bits
Default Value: 0200h Attribute: Partial Read/Write, Sticky
The PCI status register is used to record status information for PCI bus-related events. The
definition of each of the bits is given in the register bit list below. The specific implementation of
each bit in the IHPC is also given. Reads to this register behave normally. Writes are slightly
different in that bits can be reset, but not set. A bit is reset whenever the register is written and the
data in the corresponding bit location is a one (1). For instance, to clear bit 14 and not affect any
other bits, write the value 0100_0000_0000_0000b to the register.
Bits
Description
15 Detected Parity Error
This bit is set by the IHPC whenever it detects a parity error, even if parity error handling
is disabled (as controlled by bit 6 in the command register). The default value of this bit
in the IHPC is zero (0).
14 Signaled System Error
This bit is set whenever the IHPC asserts SERR#. The default value of this bit in the IHPC
is zero (0).
13 Received Master Abort
Not supported. Hardwired Value = 0
12 Received Target Abort
Not supported. Hardwired Value = 0
11 Signaled Target Abort
Not supported. Hardwired Value = 0
10:9 DEVSEL# Timing
These bits encode the timing of DEVSEL#. There are three allowable timings for
assertion of DEVSEL#. These are encoded as 00b for fast, 01b for medium, and 10b for
slow (11b is reserved). The value of these bits are always set to medium (01).
8 Data Parity Error
Not supported. Hardwired Value = 0
7 Fast Back-to-Back Capable
Not supported. Hardwired Value = 0
6:0 reserved(0)
8.1.6 RID: Revision Identification Register
Address Offset: 08h Size: 8 bits
Default Value: Stepping-Dependent Attribute: Read-Only
This register contains the revision number of the IHPC. These bits are read-only and writes to this
register have no effect.