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Intel® 460GX Chipset Software Developer’s Manual 6-5
Data Integrity and Error Handling
6.4.4 XBINIT#
XBINIT# is an input to the SAC and an output from one of the xXB’s or can also be generated by
platform logic. XBINIT# is GTL+ level, and therefore all the outputs from the xXB’s can be tied
together and fed into the SAC’s input. XBINIT# is held by the xXB until the xXB is reset, so if it
takes multiple clocks to drive from the xXB to the SAC, there should be no problem.
6.4.5 XSERR#
XSERR# is an input to the SAC. It is generated by the system from the PCI SERR# signals or for
other reasons. The system must OR all the generators together, either doing a wire-OR or adding
logic for the OR’ing function.
6.5 SAC/SDC Errors
Many errors require reading both the SAC and SDC to isolate the cause. This is because most
transactions involve both chips with a fair amount of handshaking between them. Refer to
Table 6-1 for which register holds the status information and which ones hold error logging
information. Also this table shows which errors are fatal and cause BINIT# and which are
interrupts. Also some errors are maskable.
6.5.1 Data ECC or Parity Errors
The following errors are captured by the SAC and SDC together:
• SDC Non-Fatal Error (SNE). This is set for any of the following conditions: a) double-bit ECC
error on memory b) double-bit ECC error from the system bus c) parity error on the private bus
for data d) parity error on the private bus for byte-enables e) an internal SDC ram parity error
f) a single bit correctable error on the system bus or g) the 2nd or subsequent single-bit
memory ECC errors that are not recorded by the SDC as the first 1x error. On this error
software must read the SDC to determine the type of error that was found. If the SDC reports
only single bit errors, then the SNE bit was set for a 2nd or later single-bit memory error. Once
the SDC’s error registers are cleared, the first single-bit memory error is recorded as a SCME,
and then later ones are SNE.
• SDC Correctable Memory Error (SCME). This is set on the first single-bit ECC error when
reading DRAM. The error is always corrected before being passed on to the next interface.
Since soft memory errors are not un-common, this bit has its own mask enable/disable. NOTE:
if the SDC were to receive a single bit failure from both the A and B memory boards on the
same clock, then FERR(SCME) and NERR(SCME) would be set. Otherwise, because only the
first correctable error is reported as SCME, NERR(SCME) should not be set. This assumes
that the SAC and SDC have their error registers cleared correctly. If the SDC has it’s error
registers cleared before the SAC and in between this time there is a new 1x memory error, then
the SAC_NERR(SCME) bit would get set.
• SDC Fatal Error. This is set when the SDC detects conditions that will cause an unconditional
BINIT#. The exact cause must be read from the SDC. This is set for parity errors on the
control interface between the SAC and SDC or for protocol errors.