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LPC/FWH Interface Configuration
11-2 Intel® 460GX Chipset Software Developer’s Manual
11.1.3 PCICMD–PCI Command Register (Function 0)
Address Offset: 04–05h
Default Value: 0007h
Attribute: Read/Write
This 16-bit register provides basic control over the IFB's ability to respond to PCI cycles.
11.1.4 PCISTS–PCI Device Status Register (Function 0)
Address Offset: 06–07h
Default Value: 0280h
Attribute: Read/Write
The PCISTS Register reports the occurrence of a PCI master-abort by the IFB or a PCI target-abort
when the IFB is a master. The register also indicates the IFB DEVSEL# signal timing.
Bit Description
15:10 Reserved.
9 Fast Back-to-Back Enable (Not Implemented). This bit is hardwired to 0.
8 SERR# Enable (SERRE). 1=Enable. 0=Disable. When enabled (and DLC Register, bit 3=1),
a delayed transaction time-out causes the IFB to assert the SERR# signal. The PCISTS
register reports the status of the SERR# signal.
7:5 Reserved.
4 Postable Memory Write Enable (Not Implemented). This bit is hardwired to 0.
3 Special Cycle Enable (SCE). 1=Enable, the IFB recognizes Shutdown special cycle.
0=Disable, the IFB ignores all PCI Special Cycles.
2 Bus Master Enable (Not Implemented). The IFB does not support disabling its Function 0
bus master capability. This bit is hardwired to 1.
1 Memory Access (Not Implemented). The IFB does not support disabling Function 0 access
to memory. This bit is hardwired to 1.
0 I/O Space Access Enable (Not Implemented). The IFB does not support disabling its
Function 0 response to PCI I/O cycles. This bit is hardwired to 1.
Bit Description
15 Detected Parity Error (Not Implemented). Read as 0.
14 Signaled SERR# Status (SERRS)–R/WC. When the IFB asserts the SERR# signal, this bit is
set to 1. Software clears this bit by writing a 1 to it.
13 Master-Abort Status (MAS)–R/WC. When the IFB, as a master (for Function 0), generates a
master-abort, MAS is set to a 1. Software sets MAS to 0 by writing a 1 to this bit location.
12 Received Target-Abort Status (RTA)–R/WC. When the IFB is a master on the PCI Bus (for
Function 0) and receives a target-abort, this bit is set to a 1. Software sets RTA to 0 by writing
a 1 to this bit location.
11 Signaled Target-Abort Status (STA)–R/WC. This bit is set when the IFB LPC bridge Function
is targeted with a transaction that the IFB terminates with a target abort. Software sets STA to
0 by writing a 1 to this bit location.
10:9 DEVSEL# Timing Status (DEVT)–RO. The IFB always generates DEVSEL# with medium
timing for Function 0 I/O cycles. Thus, DEVT=01. This DEVSEL# timing does not include
Configuration cycles.