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Intel® 460GX Chipset Software Developer’s Manual 5-5
Memory Subsystem
5.2.1 Summary of Configuration Rules
The memory system may populate any row in any order. There are preferred ways of populating
the memory subsystem for performance, but all configurations will work.
The following rules summarize the way the memory system may be built up. The one hard rule is
that a given row must be populated with 4 of the same DIMMs. There is no mixing allowed within
a row. If the 4 DIMMs within a row are not the same, there is no guarantee as to system behavior,
or that the system will even work.
• For each memory row, 4 DIMMs must be populated as a unit.
• The entire row must be populated with the exact same type of DIMM i.e. the same size,
number of sides, technology (16Mb vs. 64 Mb), etc.
• Different rows may use different size DIMMs (2Mx72 in row 1 and 4Mx72 in row 2).
• Different rows may mix x4 and x8 DRAMs.
• Different rows may mix double sided and single sided DIMMs.
• Any combination of rows may be populated in any order, though performance will be affected
by how the rows are populated.
• For highest performance, the total amount of memory in each stack should be the same.
• Either one or both memory cards can be populated in the system.
• Any number from 0 to 8 memory rows on a card can be populated in the system.
5.2.2 Non-uniform Memory Configurations
The example in Figure 5-2 has all the memory rows populated and all rows have the same size
DIMMs. There is no requirement that memory be populated evenly. Some stacks may have fewer
populated rows than others and the sizes within each stack may differ. Performance will be optimal
with evenly populated rows. Knowing that users may not populate the card optimally, the 460GX
will attempt to spread addresses out as best it can in an unevenly populated system.
For an easy example, use the example above, and assume that there are 4 rows of memory such that
the first row of the first 3 stacks are populated with 4Mx72 DIMMs and the last stack has only
2Mx72 DIMMs; for a total of 448 MB. The addresses are broken up such that the first 256 MB are
interleaved on a 4 way basis. The remaining 192 MB is interleaved on a 3 way basis; since all the
addresses to the last (2Mx72 row) row have been used.
This algorithm is extended for multiple sizes and arrangements of populated rows. Each row is
broken into multiple chunks and the least common denominator is found across stacks. Whatever
the system configuration, there will be some level of interleaving between cards to increase
parallelism.
5.3 Bandwidth
Sustained bandwidth is a function of traffic patterns as well as the system design and configuration.
Each memory port can transfer 16 bytes per clock. This is a peak of 2.13 GB/s per port.